This invention relates generally to circuits for adapting input - output (I/O) controllers to exchange data with a variety of different peripheral devices in various bit-parallel formats.
Presently known I/O controllers are adaptable for transferring varied length data arrays between devices and storage in a host processing system in response to programmable I/O commands which define the data length and host storage space. Generally, the data is interchanged in a predetermined bit-parallel format at the interface between the controller and each device. However, it has been found that a need exists for enabling controllers to vary such formats relative to individual devices on a dynamic (i.e. time-varying) basis, and particularly under the supervision of I/O commands. The basis for this need is that certain multiplex DI/DO operations require greater controller versatility. Such operations are illustrated herein and in the copending Heath et al application previously cross-referenced.
Accordingly, an object of this invention is to provide a more versatile interface adapter for adapting dynamically to a variety of bit-parallel formats at an associated device interface. An ancillary object is to provide for such adaptation to be governable by host-programmable command functions.
Known I/O controllers contain microprocessors and adapters which are unable to vary data communication formats to permit simultaneous communication between a device and both a host processor and the controller microprocessor. It is now recognized that a need exists for providing this capability.
An object of the present invention is to provide a more versatile interface adapter which can be conditioned dynamically, under supervision of programmable I/O commands, to transfer data in various bit-parallel formats between devices and both a host processor and a microprocessor. Another object is to provide an adapter for this purpose which can operate autonomously and thereby ease traffic burdens on associated microprocessor and host processor systems.
One presently known I/O controller system contains a microprocessor and a cycle stealing bus circuit for conducting high speed data transfers relative to a host processor. In response to I/O commands prepared by the host system, the microprocessor prepares the bus circuit. Then dedicated controls take over and operate the bus circuit to transfer data between the host processor and a device in a so-called "cycle stealing" mode. This is accomplished autonomously, i.e. without further assistance from or control by the host processor or microprocessor. While the bus circuit is transferring the data the microprocessor is potentially free for performing other functions, including retrieval and interpretation of other commands. A system of this type is disclosed in U.S. Pat. No. 4,246,637 to Brown et al.
An object of the present invention is to provide a more versatile peripheral adapter circuit which can transfer data concurrently between a device and both a bus circuit of the type described in the aforementioned Brown et al patent and an associated microprocessor, whereby the device may be linked concurrently with the microprocessor and host systems, or separately with each system, and thereby sustain several unique data processing operations.
For example, in one such operation--referred to herein as "array indexing"--a section of the adapter transfers a variable number of bit-parallel "address" data terms from the microprocessor to a device while another section of the adapter concurrently transfers "addressed" portions of a data array between the foregoing bus circuit and the same device.
In another operation of this kind, "polling" or "scanning" information is presented at the peripheral interface for selecting one of a plurality of devices and data is transferred between that device and either the host processor or microprocessor. This operation is useful in multiplex process control applications--e.g. for scanning process sensors and actuating process control elements--or in telephone line scanning operations, or the like. The microprocessor may direct such operations in an off-line (secondary) processing mode, leaving the host processor free to perform other data processing functions. A system operating in this manner is disclosed in the copending application by Heath et al, cited above under "Cross References to Related Applications".
Accordingly, another object of the present invention is to provide a more versatile interface adapter circuit which is capable of communicating with more than one programmable processing system at a time--e.g. with the foregoing microprocessor and host systems--and which can be dynamically conditioned to operate in various communication modes and bit-parallel formats under the direction of programmable commands which can be scheduled by the host system and interpreted by the microprocessor.